1. Field of the Invention
The present invention relates to a technique of designing and producing a semiconductor integrated circuit. In particular, the present invention relates to a technique of designing and producing a semiconductor integrated circuit based on a statistical model.
2. Description of Related Art
In a manufacturing stage of a semiconductor integrated circuit, physical parameters and electrical characteristics of an element such as a transistor generally vary from their design values. Such variations are called manufacturing variability. In order to ensure a normal operation of the manufactured semiconductor integrated circuit, it is important to take the manufacturing variability into consideration at a circuit design/verification stage.
For example, according to a typical STA (Static Timing Analysis), a timing analysis is performed by using a delay value at a corner condition (worst condition). That is to say, a certain margin corresponding to the manufacturing variability is taken into consideration. By designing the circuit such that given timing constraints are met even under the corner condition, delay variations caused by the manufacturing variability can be absorbed. However, to design the circuit such that the given timing constraints are met even under the corner condition leads to increase in design time.
Therefore, it has been proposed in recent years to introduce “statistical approach” to the circuit design/verification in order to treat the manufacturing variability more efficiently and optimize the design margin.
A method of statistically expressing model parameters (SPICE model parameters) used in the SPICE (Simulation Program with Integrated Circuit Emphasis) is described in a paper: Kiyoshi Takeuchi and Masami Hane, “A Highly Efficient Statistical Compact Model Parameter Extraction Scheme”, SISPAD 2005, 1-3 Sep. 2005, pp. 135-138. More specifically, a principal component analysis is performed with respect to I-V characteristics of a plurality of samples to determine statistical model parameters. The statistical model parameters are used in the SPICE simulation, and thereby the simulation accuracy is improved.
A similar method is also disclosed in PCT Publication No. WO02/059740. Statistical model parameters are determined by a principal component analysis. Here, global manufacturing variability between chips and local manufacturing variability (OCV: On-Chip Variation) within a chip are considered separately from each other.
Japanese Laid-Open Patent Application No. 2005-92885 discloses a method of SSTA (Statistical STA). More specifically, a delay model of a cell is given by a linear function. The linear function is a function of delay variation factors. The cell delay model is used to perform the statistical (stochastic) timing analysis.
Japanese Laid-Open Patent Application No. 2000-181944 discloses a method of creating a cell delay library. First, cell delay values at various conditions are calculated by performing a circuit simulation. Next, a RSF (Response Surface Function) that expresses the cell delay value is generated by using the least squares method. Moreover, coefficients of the RSF are corrected by referring to actual measurement data.
The inventors of the present application have recognized the following points. The statistical approach that can efficiently treat the manufacturing variability is indispensable for improving accuracy and reducing time of the circuit design/verification. To this end, it is important to model the elements and cells by considering the manufacturing variability statistically. Such modeling in which the manufacturing variability is statistically considered is referred to as “statistical modeling” hereinafter.
Meanwhile, a manufacturing process of the semiconductor integrated circuit is progressing from day to day. With maturation of the manufacturing process, the manufacturing variability is supposed to be improved. When the manufacturing variability is improved, it is possible to reduce the margin to be considered in the circuit design/verification. This leads to reduction in the circuit area and power consumption. It is therefore desirable to perform the statistical modeling of the cell again in accordance with the maturation of the manufacturing process.
Moreover, there may be a case where impurity concentrations of wells and diffusion layers are adjusted and thus the transistor characteristics are changed. It is desirable to perform the statistical modeling of the cell again also in such a case where the manufacturing process is purposely changed.
However, the modeling (characterization) of the cell requires tremendous amounts of processes, time and costs. If re-characterization is not performed in order to save the time and costs, it means that the latest manufacturing process is not reflected in the circuit design/verification. In other words, even when the manufacturing variability is improved due to the maturation of the manufacturing process, the margin to be considered in the circuit design/verification is unchanged and thus the effects of reduction in the circuit area and power consumption cannot be obtained. This means that the semiconductor integrated circuit is unable to demonstrate its true abilities corresponding to the maturity of the manufacturing process.
Therefore, a technique is desired that can “update” the statistical cell model (statistical cell library) easily without performing the re-characterization when the manufacturing process is changed. In other words, a technique is desired that can promptly update the statistical cell model in accordance with the maturation and intended change of the manufacturing process.